MIS-type field-effect transistors (hereinafter abbreviated as MISFET) are commonly formed on group IV semiconductor substrates. The term “group IV semiconductor” refers to Ge, C, Si, and mixed crystals thereof. These group IV semiconductors are superior with regard to mechanical strength, cost, and micromachining properties compared to other semiconductors, and are adapted for creation of large-scale integrated circuits, which are the primary application of a MISFET.
Among group IV semiconductors, Si substrates in particular are most commonly used in MISFET fabrication. Some reasons for this are that SiO2 gate insulating films are easily formed on an industrial scale, and that the SiO2/Si interface characteristics are good.
However, Si suffers from low electron-hole mobility compared to other semiconductors. This is caused by silicon's characteristic band structure. Low mobility causes the channel resistance of a MISFET to increase, which leads to decreased switching speed in the MISFET. Techniques have therefore been proposed for changing the band structure while using Si as the channel material of a MISFET, and enhancing the electron-hole mobility (see Japanese Laid-open Patent Application Nos. 10-270685 and 2002-237590, for example). These methods involve straining the Si.
FIG. 17 shows a method for fabricating strained Si. First, a base substrate is prepared that is composed of Si1−xGex (wherein 0<x≦1; hereinafter abbreviated as SiGe), which has a larger atomic spacing than Si. A thin film of Si is then epitaxially grown on this SiGe base substrate so as to create a matched lattice. The Si is then subjected to biaxial tensile strain, and the band structure is changed. The phonon dispersion and the effective mass of electrons and holes are thereby reduced, and the electron-hole mobility is increased in comparison to unstrained Si.
FIGS. 18A and 18B show the relationship between the rate of increase in electron-hole mobility and the Ge concentration (×100[%]) of the SiGe base substrate. In the diagrams, the solid and dashed curves indicate calculated values, and the plotted points indicate the experimental values. Since the atomic spacing of the Si1−xGex crystals in the base substrate is substantially proportional to the Ge concentration, the amount of strain in the Si increases as the Ge concentration increases. It is apparent from these diagrams that the mobility of both electrons and holes can be increased by a factor of 1.5 or higher compared to unstrained silicon by applying a strain to the Si.
The method for manufacturing a strained-Si channel MISFET according to the conventional technique will next be described with reference to FIGS. 19A through 19C and FIGS. 20A and 20B. First, a strained Si layer 2 is epitaxially grown on a base SiGe layer 1 (FIG. 19A). A gate insulating film 3 and a gate electrode film 4 are then grown on this strained Si layer 2 (FIG. 19B), after which patterning is performed, and a gate insulating film 3a and gate electrode 4a are formed (FIG. 19C). Using the gate electrode 4a as a mask, an impurity is introduced by an ion implantation method into the regions in which the source and drain are to be formed inside the strained Si layer 2. The dose at this time is 1×1015 cm−2 or higher. This high-dose ion implantation is performed in order to sufficiently lower the contact resistance and the parasitic resistance between source and drain. An amorphous layer 5 is formed on the strained Si layer 2 by this type of high-dose ion implantation (FIG. 20A). Heat treatment is then performed in order to activate the impurity, whereupon the amorphous layer 5 crystallizes while undergoing solid-phase growth, and a source/drain region 6 is formed (FIG. 20B).
FIG. 21 shows the electrical characteristics of a strained-Si channel MISFET having a gate length of 1 μm created according to this method. This transistor has good electrical characteristics, and no abnormal leak currents or the like are observed.
Patent document 1: Japanese Unexamined Patent Publication hei-10-270685
Patent document 2: Japanese Unexamined Patent Publication 2002-237590
Non-Patent document 1: H. C.-H. Wang et al., “Substrate-Strained Silicon Technology: Process Integration”, IEDM 2003, Technical Digest, pp. 61-64
Non-Patent document 2: Applied Physics, vol. 65, No. 11, p. 1131 1996, Ion Implantation Technology Proceedings vol. 2, p. 744 1999